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ADE7518
PHASE COMPENSATION
The ADE7518 must work with transducers that can have
inherent phase errors. For example, a phase error of 0.1° to 0.3°
RMS CALCULATION
The root mean square (rms) value of a continuous signal V(t) is
defined as
∫
is not uncommon for a current transformer (CT). These phase
errors can vary from part to part, and they must be corrected to
perform accurate power calculations. The errors associated with
phase mismatch are particularly noticeable at low power factors.
V rms =
1
T
T
× V 2 ( t ) dt
0
(1)
The ADE7518 provides a means of digitally calibrating these
small phase errors. The part allows a small time delay or time
advance to be introduced into the signal processing chain to
compensate for small phase errors. Because the compensation is
in time, this technique should only be used for small phase
errors in the range of 0.1° to 0.5°. Correcting large phase errors
using a time shift technique can introduce significant phase
errors at higher harmonics.
For time sampling signals, rms calculation involves squaring the
signal, taking the average, and obtaining the square root. The
ADE7518 implements this method by serially squaring the input,
averaging them, and then taking the square root of the average.
The averaging part of this signal processing is done by implement-
ing a low-pass filter (LPF3 in Figure 47, Figure 48, and Figure 50).
This LPF has a ?3 dB cutoff frequency of 2 Hz when MCLK =
4.096 MHz.
The phase calibration register (PHCAL[7:0]) is a twos complement,
signed, single-byte register that has values ranging from 0x82
(?126d) to 0x68 (+104d).
The PHCAL register is centered at 0x40, meaning that writing
V ( t ) = 2 × V sin( ω t )
where V is the rms voltage.
V 2 ( t ) = V 2 ? V 2 cos ( 2 ω t )
(2)
(3)
0x40 to the register results in 0 delay. By changing this register,
the time delay in the voltage channel signal path can change
from ?231.93 μs to +48.83 μs (MCLK = 4.096 MHz). One LSB
is equivalent to a 1.22 μs (4.096 MHz/5) time delay or advance.
A line frequency of 60 Hz gives a phase resolution of 0.026° at
the fundamental (that is, 360° × 1.22 μs × 60 Hz).
Figure 46 illustrates how the phase compensation is used to
When this signal goes through LPF3, the cos(2ωt) term is attenu-
ated and only the dc term V rms2 goes through (shown as V 2 in
Figure 47).
V 2 ( t ) = V 2 – V 2 cos (2 ω t )
V ( t ) = √ 2 × V sin( ω t )
LPF3
remove a 0.1° phase lead in the current channel due to the
external transducer. To cancel the lead (0.1°) in the current
INPUT
V
channel, a phase lead must also be introduced into the voltage
channel. The resolution of the phase adjustment allows the
introduction of a phase lead in increments of 0.026°. The phase
lead is achieved by introducing a time advance into the voltage
channel. A time advance of 4.88 μs is made by writing ?4 (0x3C)
to the time delay block, thus reducing the amount of time delay
by 4.88 μs, or equivalently, a phase lead of approximately 0.1° at a
line frequency of 60 Hz (0x3C represents ?4 because the register is
centered with 0 at 0x40).
V 2 ( t ) = V 2
Figure 47. RMS Signal Processing
The I rms signal can be read from the waveform register by setting
the WAVMODE register (0x0D) and setting the WFSM bit in
the Interrupt Enable 3 SFR (MIRQENH, 0xDB). Like the current
and voltage channels waveform sampling modes, the waveform
data is available at a sample rate of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS,
or 3.2 kSPS.
I P
HPF
24
It is important to note that when the current input is larger than
I
PGA1
ADC 1
40% of full scale, the I rms waveform sample register does not
I N
24
LPF2
represent the true processed rms value. The rms value processed
with this level of input is larger than the 24-bit read by the wave-
V
V P
V N
PGA2
ADC 2
1
7
DELAY BLOCK
1.22μs/LSB
0
CHANNEL 2 DELAY
REDUCED BY 4.48μs
(0.1°LEAD AT 60Hz)
0x0B IN PHCAL[7:0]
V
form register, making the value read truncated on the high end.
V
1 0 0 1 0 1 1 1
I
I
0.1°
PHCAL[7:0]
–231.93μs TO +48.83μs
60Hz
60Hz
Figure 46. Phase Calibration
Rev. 0 | Page 46 of 128
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